
Scaler
Definition: The term scaler, as used in IS-95, is defined to be the precision digital multiplier which amplitude scales the I and Q components of each of the forward-link channels and the Digital-to-Analog converter used prior to the signals being combined and input to the Linear Power Amplifier (LPA).
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Scaler
Application: There is a considerable degree of precise power control on the forward link in IS-95. On a frame-by-frame basis, the power is controlled by factors of two in accordance with the bit rate generated by the variable rate Vocoder. Within the frame, the power-control bits are transmitted at a power level at least as high as that used by the full-rate frames. It's not unusual for the power control bits to be transmitted at a power level above the full-rate frames. In addition, the overall power level around which the frame-by-frame adjustments are made also varies in accordance with the forward-link power control loop. Hence, each individual channel is separately power controlled. Each traffic channel typically takes on two power levels several times during each frame and the power may vary from frame-to-frame. All this power control has to be done fairly precisely and ideally without the problems usually associated with analog multipliers. In IS-95, although the standard itself does not give any details, this scaling requirement is typically done in a digital multiplier or gain device called the scaler.
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Scaler
Example: One input to the scaler is the digital I and Q masked and PN spread Walsh code word generated at the output of the baseband digital 48-tap FIR filter in the quadrature PN spreader associated with each forward-link channel. Aside from the ripple caused by the FIR filter, these digital signals may be assumed to have a value of either plus or minus one. These "unit" magnitude digital signals I and Q must be scaled to achieve their proper power levels. To do this, the second input to the scaler is a digital factor K(t), which var-ies over time under the control of the base station. A quadrature scaler performs a digital multiply and outputs digital signals IxK(t) and QxK(t). Each IxK(t) digital word is input to a Digital-to-Analog (D/A) converter, whose output is an analog signal I(t) whose voltage is proportional to K(t). The same is true of an analog signal Q(t) derived from QxK(t). Typically all the scaled I(t) signals are added together and all the scaled Q(t) analog signals are added together to form aggregate signals, which may be called ISUM(t) and QSUM(t) signals. The aggregate signals ISUM(t) and QSUM(t) are amplified by the LPA. The output is a Quadrature Phase Shift Keyed (QPSK) signal with varying envelop with each individual channel appropriately scaled.
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